Once a newly designed integrated circuit has been formed on a semiconductor substrate, the integrated circuit must be thoroughly tested to ensure that the circuit performs as designed. Portions of the integrated circuit that do not function properly are identified so that they can be corrected by modifying the design of the integrated circuit. This process of testing an integrated circuit to identify problems with its design is known as debugging. After debugging the integrated circuit and correcting any problems with its design, the final fully functional integrated circuit designs are used to mass produce the integrated circuits in a manufacturing environment for consumer use.
During the debugging process, it is sometimes necessary to probe certain internal electrical nodes in the integrated circuit in order to obtain important electrical data from the integrated circuit, such as for example voltage levels, timing information, current levels, thermal information or the like. The typical integrated circuit device contains multiple layers of metal interconnects. The metal interconnects in the first layer of an integrated circuit device generally carry the most valuable electrical data for debugging purposes. Metal interconnect lines in the first metal layer reside closest to the semiconductor substrate and are usually directly coupled to important components of the integrated circuit device such as for example transistors, resistors and capacitors. It is the electrical data received, manipulated and transmitted by these components that a designer is most interested in analyzing during the debugging process.
FIG. 1A is an illustration of an integrated circuit package 101 that includes wire bonds 103 disposed along the periphery of integrated circuit die 105 to electrically connect integrated circuit connections through metal interconnects 113 to pins 107 of package substrate 111. As shown in FIG. 1A, metal interconnects 113 are coupled to diffusion regions 117 through metal contacts 109. In some instances, diffusion regions 117 may be used in integrated circuit devices such as transistors, resistors, capacitors or the like. As shown in FIG. 1A, a probe tool 115 may be used to probe metal interconnect 113 through the top side 119 of integrated circuit die 105 to obtain the electrical data from integrated circuit die 105.
In some instances, probe tool 115 may be a mechanical probe tool that is used to directly probe a signal of interest from integrated circuit package 101. A mechanical probe is commonly used to directly probe important signals of interest that have been routed to a layer of metal interconnects 113 near the front side 119 of the integrated circuit die 105. When using a mechanical probe tool 115 to probe signals, the mechanical probe tool is placed in direct physical contact with the metal interconnect 113 carrying the signal of interest.
There are several disadvantages with the wire bond design of integrated circuit package 101 of FIG. 1A. One problem stems from the fact that as the density and complexity of integrated circuit die 105 increases, so must the number of wire bonds 103 required to control the functions integrated circuit die 105. However, there are only a finite number of wire bonds 103 that can fit along the periphery of integrated circuit die 105. One way to fit more wire bonds 103 along the periphery of integrated circuit die 105 is to increase the overall size of integrated circuit die 105, thereby increasing its peripheral area. Unfortunately, an increase in the overall size of integrated circuit die 105 also significantly increases the integrated circuit manufacturing costs.
Another disadvantage with integrated circuit package 101 of FIG. 1A is that the active circuitry within integrated circuit die 105 must be routed through electrical interconnects 113 to the peripheral region of integrated circuit die 105 in order to electrically couple the active circuitry to wire bonds 103. By routing these metal interconnect lines 113 over a relatively long distance across the integrated circuit die 105, the increased resistive, capacitive and inductive effects of these lengthy interconnects 113 result in an overall speed reduction of the integrated circuit. In addition, the inductance of wire bonds 103 may also severely limit high frequency operation of integrated circuit devices in integrated circuit package 101.
With continuing efforts in the integrated circuit industry to increase integrated circuit speeds as well device densities, there is a trend towards using flip-chip technology when packaging complex high speed integrated circuits. Flip-chip technology is also known as controlled collapse chip connection (C4) packaging. In flip-chip packaging technology, the integrated circuit die is flipped upside-down. This is opposite to how integrated circuits are packaged today using wire bond technology, as illustrated in FIG. 1A. By flipping the integrated circuit die upside-down, ball bonds may be used to provide direct electrical connections from the bond pads directly to the pins of a flip-chip package.
To illustrate, FIG. 1B shows a flip-chip package 151 with an integrated circuit die 155 flipped upside-down relative to the wire bonded integrated circuit die 105 of FIG. 1A. In comparison with wire bonds 103 of FIG. 1A, ball bonds 153 of flip-chip package 151 provide more direct connections between the circuitry integrated circuit die 155 and the pins 157 of package substrate 161 through metal interconnects 159. As a result, the inductance problems that plague typical wire bond integrated circuit packaging technologies are reduced. Unlike wire bond technology, which only allows bonding along the periphery of the integrated circuit die 155, flip-chip technology allows connections to be placed anywhere on the integrated circuit die surface. This results in reduced inductance power distribution to the integrated circuit, which is another major advantage of flip-chip technology.
One consequence of integrated circuit die 155 being flipped upside-down in flip-chip package 151 is that access to the internal nodes of integrated circuit die 155 for debugging purposes has become a considerable challenge. As discussed above, the present day debug process for wire bond technology is based in part on directly probing the metal interconnects through the front side of the integrated circuit die with a mechanical probe tool. However, with flip-chip packaging technology, this front side methodology is not feasible since the integrated circuit die is flipped upside-down. For example, as illustrated in FIG. 1B, access to the metal interconnects 159 for the purpose of conventional mechanical probing is obstructed by the package substrate 161. Instead, the P-N junctions forming diffusion regions 163 of the integrated circuit are accessible through the back side 165 of the semiconductor substrate of integrated circuit die 155.
In view of the foregoing, what is desired is a method and an apparatus providing a mechanical probe structure in an integrated circuit. Such a method and apparatus should allow the mechanical probing of signals through the back side of modern day flip-chip packaged integrated circuits.